1. Field of the Invention
The present invention relates to a semiconductor apparatus, more particularly to a semiconductor apparatus used as an element that controls an inverter for driving a motor or the like.
2. Description of Related Art
A high voltage integrated circuit (HVIC) is a semiconductor apparatus used as, for example, an element that controls power devices in an inverter for driving a load such as a motor or the like.
One example of a circuit for driving an inverter is described below with reference to FIG. 14. The circuit includes a first element 303, a second element 304, photocouplers 305a, 305b as level-shift elements 305a, 305b, and a control circuit 306. The first element can function as a high potential reference circuit part for driving insulated gate bipolar transistors (IGBTs) 302a provided in a high-side of an inverter circuit 301 for driving a motor 300. The second element can function as a low potential reference circuit part for driving IGBTs 302b provided in a low-side of the inverter circuit 301. The first element and the second element may be provided in different chips. The photocouplers 305a, 305b and the control circuit 306 are provided between the chips. In such a circuit, signals are transmitted through the photocouplers 305a, 305b to provide a level shift between the reference potentials of the high and low potential reference circuit parts.
Recently, because of the downsizing of an inverter, the above circuit has been integrated into a single chip or in other words, integrated into an HVIC. As shown in FIG. 15, an HVIC (i.e., semiconductor apparatus) 406 includes a high potential reference circuit part 403 and a low potential reference circuit part 404, which are for use in controlling IGBTs 402a, 402b of an inverter circuit 401 for driving a motor 400. The HVIC 406 further includes a level-shifting element 405 having a high breakdown voltage (e.g., LDMOS: lateral diffused metal oxide semiconductor element).
The HVIC 406 formed in a single chip has, however, a difficulty associated with potential interference between the high and low potential reference circuit parts 403, 404. Such interference causes an improper operation in the circuit. Because of the above difficulty, element isolation is made by using a junction isolation (JI) structure, a dielectric isolation structure, or a trench isolation structure with silicon on insulator (SOI) substrate (c.f., JP-A-2006-93229). However, in any one of the above-described element isolation structures, when the level is shifted from a low potential such as 0V to a high potential such as 750V, a higher potential (e.g., a potential exceeding 1200 V) generates at a large rise rate of a few tens kV/μsec, resulting in a large amplitude of potential. It is difficult to treat the above high voltage surge having the high rise rate without involving circuit malfunction. Herein, such high voltage surge having a high rise rate is referred to as a dv/dt surge since an increase in the voltage with the rise time is large. In particular, the above dv/dt surge becomes a problem in a circuit having a noise-sensitive analog-element since failure notably occurs in such a circuit more than in a logic circuit.
Discussion is given below in connection with the above points, as the related art. Out of the above-described element isolation structures, the trench isolation structure with the SOI substrate may have high resistance to noise. For element isolation, the trench isolation structure may be high potential one. However, in developing a level-shifting element with the trench isolation structure, the inventors has revealed following difficulties. When a dv/dt surge is applied in an HVIC having a trench isolation structure with a SOI substrate, potential is interfered through a support substrate, generating a displacement current that charges or discharges a parasitic capacitance formed in a buried oxide (BOX) layer between the support substrate and an active layer (i.e., an SOI layer). As a result, the circuit may improperly operate. FIG. 25 is a cross sectional diagram illustrating generation of a displacement current in an HVIC where high and low electric potential reference circuit parts HV, LV are formed in an SOI layer 511. As shown in FIG. 25, for example, a displacement current generates and flows (i) from a virtual GND potential part of the high electric potential reference circuit part HV via a buried layer 513 (i.e., box layer) into a support base 512, and (ii) flows from the support base 512 via again the buried layer 513 into a GND potential part of the low electric potential reference circuit part LV.
The above difficulties may be suppressed by reducing propagation of the displacement current in such a manner that the BOX layer is made thicker to decrease a parasitic capacitance, or an impurity concentration on a support substrate 512 side is made smaller to increase a resistance. However, when an amplifier circuit having a high amplification rating is integrated for instance, a slight displacement current can become a factor for improper operation.